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Training Classes FPGA > Universities Classes using the DE2
   
Colorado State University 
 
가    격 : 견적문의
중    량 : 1g

Lab Schedule ECE 450

WEEK

Lab Content 1 week lab Date from - Date to
1 Introduction to ECE451 tools-Cadence
Introduction to ECE451 tools-Verilog
Introduction to ECE451 tools-Altera_Board
2 weeks lab 9/13 - 9/17
3 Lab 1: Design of a 3-bit ALU (manual schematic) (cont.) 1 week lab 9/20 - 9/24
4 Lab 2: Design of a 3-bit ALU (Verilog)   1 week lab 9/27 - 10/1
5 Lab 3: Design of a Subway Control Logic (manual schematic) 1 week lab 10/4 - 10/08
6 Lab 4: Design of a Logarithmic Multiplier (Verilog) 1 week lab 10/25-10/29
7 Lab 6: Design of a Gray Scale Counter (manual schematic) 1 week lab 11/1 - 11/5
8-9 Lab 7: Design of a Pulse Clock Generator and a Pyramid Counter (Verilog) 2 week lab SKIP
10 Lab 8: Subway Signal Control Logic (manual schematic & Verilog) 2 week lab 11/8 - 11/12
111 Lab 8: Continuation of the Subway Signal Control Logic (manual schematic & Verilog) 2 of 2 11/15 - 11/19
  *** Thanksgiving break ***    
12 Lab 8: Continuation of the Subway Signal Control Logic (manual schematic & Verilog) Extension for completion of Lab 8 11/29 - 12/3
13 Lab 9: Design of a Complex Finite State Machine (Verilog part ONLY(extra credit) 1 week lab 12/6 - -12/10

In order to receive credit for the lab section, the pre-work is to be completed prior to commencement of lab and that each lab needs to be demonstrated to the TA during the week the lab is scheduled. A lab report is due at the end of each lab before starting the next lab.
Each lab report must contain:

  1. A list of items completed
  2. A list of items not completed (if any)
  3. Lab procedures
  4. Schematics and Verilog models
  5. Simulation results
  6. Analyses and explanations
  7. Conclusions
  8. Answers to questions contained in the lab

* Thanksgiving break. 
 


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