Features
- 200 MHz (400 Mbps) Cyclone memory performance
- Low cost DDR2 Memory Controller for Cyclone devices
- From 1 to 16 Avalon-MM local bus port interfaces
- Memory bandwidth utilization in excess of 95%
- Avalon Piplined and Burst transfers
- Avalon local bus width from 8 to 128-bits
- Memory data width: 8/16/32/64-bit
- Configurable FIFO depth: 16 to 2048 bytes
- Intelligent SDRAM burst caching controller minimizes wait-states
- PCB layout independent DDR2 Round-Trip capture scheme
- Requires only single PLL with 2 clock outputs
- Independent system/memory time domain clocking
- Supports Cyclone II, III, IV-E, IV-GX devices
Overview
The Microtronix Avalon Multi-port DDR2 Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II processor in Avalon® multi-master streaming data systems. Advanced design features enable maximum system clock rates using low speed FPGA's and standard memory devices, lowering your production cost, and saving you money.
The Avalon-MM slave ports can be independently clocked allowing the system to be partitioned and optimized to achieve maximum performance. Supporting post memory read and write cycles, the data FIFO's effectively double memory bandwidth on sequential address or FIFO cache hits. FIFO depth can be tailored for either streaming or random access.
The core is optimized for the Altera® Cyclone family of field programmable logic devices. The Avalon slave ports are configured with a SOPC Builder Ready component & Qsys GUI which greatly simplifies the design of Avalon-MM based SOC systems.
The SDRAM Memory Controller handles all memory tasks, including initialization and refresh cycles. It is designed to operate asynchronous to the local port clocks enabling the memory to be clocked at its peaked rated frequency maximizing system performance.
IP Core Advantages
- MegaWizzard GUI for ease of configuration
- Requires only single PLL with 2 clock outputs
- DQS data capture clocking simplifies DDR2 PCB timing constraints and eliminates dedicated data capture PLL
- Configurable FIFO maximizes performance of streaming data applications
- Configurable memory and local bus data width optimizes cost
- Independent time domain clocking optimizes memory bandwidth
- Round-robin (dafault) and user configurable bus arbitration schemes
- Synopsis TimeQuest support ensures timing closure
Other Features
- Altera SOPC Builder Ready & Qsys Configuration GUI
- Supports Synopsys TimeQuest timing analyzer
- VHDL IP functional simulations models
- On Die Termination (ODT) improves signal integrity
- Altera OpenCore Plus evaluation
License Options
- Node Locked: Supports a single user. It is tied to the NIC ID of a PC.
- Floating Server: Supports multiple users, typically 2 or 5 seats
Custom cores are available
The IP Core can be easily customized for additional bus ports or for wider data widths. Contact sales with your requirements.
