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Microtronix-FPGA Series > IP Core
   
Camera Link Trancevier IP Core 
 
가    격 : 견적문의
중    량 : 1g

Camera Link Tranceiver IP Core

Camera Link Tranceiver IP Core

   

Key Features

  • Supports Medium & Full Camera Link interfaces
  • Supports 64-bit and 80-bit extended Full configurations
  • Camera and Frame Grabber configurations
  • 7:1 Camera Link Serializer/Deserializer (SerDes)
  • Transmission clock rates to 85 MHz. in Cyclone, Stratix & Arria devices
  • Auto Link alignment of Medium and Full Camera Link sources
  • Power Over Camera Link (PoCL) SafePower
  • Bi-directional serial Camera Link communication
  • Configuration GUI streamlines design process
  • Supports: Cyclone II, III, IV, V, Arria II GX, V & Stratix III, IV, V (including GX) devices

Overview

The Microtronix Camera Link Transceiver IP Core is designed for building vision systems incorporating Camera Link™ communication interfaces including Base, Medium & Full Channel Link configurations. The core supports camera control signals, serial communication, and video data. It is designed for building both Camera and Frame Grabber devices. 

The Camera Link standard is based on Channel Link® technology developed by National Semiconductor. Channel Link uses LVDS technology for transmitting digital data using a parallel-to-serial transmitter and a serial-to parallel-receiver to transmit data at rates up to 2.38 Gbps. The base Channel Link standard uses 28 bits to represent up to 24 bits of pixel data and 3 bits for Video Sync signals. These consist of Data Valid, Frame Valid, and Line Valid bits. The data is serialized 7:1, and the four data streams and a dedicated clock are driven over five LVDS pairs. The Receiver accepts the four LVDS data streams and one LVDS clock, and then deserializes the data into 28 bits of parallel data and a clock.


Channel Link Aligner

The core provides a Channel Link Aligner block which synchronizes the data in Medium and Full Camera Link Frame Grabber configurations. This block removes delays caused by phase differences of the clock sources between links or cable length mismatches. The Link Aligner block compares the LVAL signal from each Channel Link and auto adjusts the delays through the IP to bring the links into alignment. Additionally, it synchronizes the output Ports to the STROBE/XCLK clock.


Power Over Camera Link SafePower

The Power Over Camera Link (PoCL) SafePower logic block, when combined with supported hardware, allows a Frame Grabber to provide power to PoCL cameras and still remain compatible with non-PoCL cameras. The SafePower block works with the PoCL circuitry on the Microtronix Camera Link Receiver Board.

Target Applications

The Camera Link Transceiver IP Core is specifically targeted at industrial video applications including; industrial vision systems, high-speed video interconnects, Camera Link frame grabber devices, interface conversion, and video processing equipment. 

Other Features and Deliverables

The IP is supplied as an FTP download. It includes:
  • Java Configuration GUI
  • TimeQuest timing analyzer Synopsis Design Constraint (SDC) file
  • VHDL ModelSim library
  • User documentation
  • Quartus Reference Design supporting a Camera Link Base, Medium & Full configurations
  • Includes perpetual IP core license with 1 year of updates
A 30-day Altera OpenCore Plus evaluation license available. (Use the request link above.)

License Options

The IP Core license is perpetual and does not expire. It is available either as a Node Locked or Floating Server.

  • Node Locked: Supports a single user. It is tied to the NIC ID of a PC.
  • Floating Server: Supports multiple users (typically 2 or 5 seats)
 


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