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Terasic > FPGA Board > Arria 2 GX
Arria II GX Video Development System 
    : 2,800g


The Arria II GX Video Development System is an ideal video processing platform for high-end video applications. Terasic recognized for its strong design expertise in high-end video, imaging and multimedia products have made available a video development package that targets video processing development using an Arria II GX device. The package includes an Arria II GX FPGA development kit (DK-DEV-2AGX125N) featuring an EP2AGX FPGA device with HSMC connectors to allow additional functionality and connectivity via HSMC daughter boards. The Arria II GX FPGA development kit delivers a complete PCI Express-based development platform. This interface uses the Arria II GX devices PCI Express hard IP to accelerate development time for high-volume PCI Express applications including add-in cards, host bus adapters, graphics cards, and high-end servers. Furthermore, the board includes an abundant amount of memory including on-board DDR3 device and DDR2 SODIMM, creating a complete integrated memory interface solution for memory-intensive applications.

The DVI-HSMC daughter card part of the bundled package will allow developers to access high quality and high resolution video signals that can support resolution up to 1600x1200. A complete DVI video controller design with source code is provided.

The development can also allow users to experience advanced image processing designs incorporating VIP (Alteras Video and Image Processing Suite MegaCore Functions).

Arria II GX Development Board:


         124,100 logic elements (LEs)

         49,640 adaptive logic modules (ALMs)

         8,121 Kb on-chip memory

         12 high-speed transceivers

         6 phase-locked loops (PLLs)

         576 18x18 multipliers

         0.9V core power

Max II EPM2210F256 CPLD

         2.5V core power

On-board ports

         One HSMC expansion port

         One gigabit Ethernet port

PCI Express x8 Edge Connector

         Support connection speed of Gen1 at 2.5Gbps/lane

         Connection established with PC motherboard with x8 PCI Express slot

On-board Memory

         128MB 16bit DDR3 device

         1GB 64bit DDR2 SO-DIMM

         2MB SSRAM

         64MB FLASH

FPGA Configuration Circuitry

         MAX II CPLD and flash fast passive parallel configuration

         On-board USB-Blaster circuitry using the Quartus II Programmer

On-board Clocking Circuitry

         Four on-board oscillators

o    100MHz

o    Programmable oscillator, default frequency 125MHz

o    Programmable oscillator, default frequency 100MHz

o    155.52MHz

         SMA connectors for external LVPECL clock input

         SMA connector for clock output

General User I/O


o    Four user LEDs

o    Two-line character LCD display

o    One configuration-done LED

o    One HSMC interface transmit/receive LED (Tx/Rx)

o    Three PCI Express LEDs

o    Five Ethernet LEDs


         One user reset (CPU reset)

         One MAX II CPLD reset

         One load image (program FPGA from flash)

         One image select (select image to load from flash)

         Two general user push-buttons

 DIP Switches

         Four user DIP switches

         Eight MAX II device control DIP switches


Power Supply

         14V to 20V DC input

         PCI Express edge connector power

         On-board power measurement circuitry

Arria II GX FPGA Development Kit CD-ROM

         Design examples

o    Board Update Portal, featuring the Nios II processor web server and remote system update

o    Board test system

Altera's Complete Design Suite DVD

         Quartus II Software Development Kit Edition, includes support for Arria II GX FPGAs

o    Quartus II software license is not included as part of this kit

         Nios II Embedded Design Suite

         MegaCore IP Library includes PCI Express, Triple Speed Ethernet, SDI, and DDR3 High-Performance Controller IP cores

IP evaluation available through OpenCore Plus


Digital Transmitter

         One DVI transmitter with single transmitting port

         Digital Visual Interface (DVI) Compliant

         Supports resolutions from VGA to UXGA (25 MHz – 165 MHz Pixel Rates)

         Universal Graphics Controller Interface

o    12-Bit, Dual-Edge and 24-Bit, Single-Edge Input Modes

o    Adjustable 1.1 V to 1.8 V and Standard 3.3 V CMOS Input Signal Levels

o    Fully Differential and Single-Ended Input Clocking Modes

o    Standard Intel 12-Bit Digital Video Port Compatible as on Intel 81x Chipsets

         Enhanced PLL Noise Immunity

o    On-Chip Regulators and Bypass Capacitors for Reducing System Costs

         Enhanced Jitter Performance






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