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Terasic-FGPA Series > All FPGA Main Board > Arria II. V
   
Arria II GX-260 FPGA Development Board 
 
가    격 : 견적문의
중    량 : 100g

  

The Arria II GX-260 FPGA development board provides a hardware platform that features sixteen 6.375Gbps transceivers and up to 1.25Gbps LVDS support, making them suitable for a broad array of applications in markets that include wireless, wireline, test, medical, and storage. With the Arria II GX-260 FPGA, customers can achieve the power-reduction benefits, while providing high functionality for applications with significantly higher bandwidth requirements. The device features 256,000 logic elements (LEs), 11.7Mb of embedded memory, and 612 I/Os. Furthermore, the board delivers an abundant set of on-board memory consisting of DDR2 and DDR3 memory. With protocol reference designs and an Arria II GX-260 FPGA development kit, designers can easily begin developing and prototyping their designs immediately.

 * Memory Solution for Altera FPGAs
     
 

Arria II GX-260 FPGA development board

Arria II GX EP2AGX260 FPGA

  • 256,000 logic elements (LEs)
  • 102,600 adaptive logic modules (ALMs)
  • 11,756 Kb on-chip memory
  • 16 high-speed transceivers
  • 6 phase-locked loops (PLLs)
  • 736 18x18 multipliers
  • 0.9V core power

Max® II EPM2210F256 CPLD

  • 2.5V core power

On-board Ports

  • Two HSMC expansion ports
  • One gigabit Ethernet port

PCI Express x8 Edge Connector

  • Support connection speed of Gen1 at 2.5Gbps/lane
  • Connection established with PC motherboard with x8 PCI Express slot

On-board Memory

  • 128MB 16bit DDR3 device
  • 1GB 64bit DDR2 SO-DIMM
  • 2MB SSRAM
  • 64MB FLASH

FPGA Configuration Circuitry

  • MAX II CPLD and flash fast passive parallel configuration
  • On-board USB-Blaster™ circuitry using the Quartus II Programmer

On-Board Clocking Circuitry

  • Four on-board oscillators
    • 100MHz
    • Programmable oscillator, default frequency 125MHz
    • Programmable oscillator, default frequency 100MHz
    • 155.52MHz
  • SMA connectors for external LVPECL clock input
  • SMA connector for clock output

General User I/O

  • LEDs/displays
    • Four user LEDs
    • Two-line character LCD display
    • One configuration-done LED
    • One HSMC interface transmit/receive LED
    • Three PCI Express LEDs
    • Five Ethernet LEDs

Push-buttons

  • One user reset (CPU reset)
  • One MAX II CPLD reset
  • One load image (program FPGA from flash)
  • One image select (select image to load from flash)
  • Two general user push-buttons

DIP switches

  • Four user DIP switches
  • Eight MAX II device control DIP switches

Power Supply

  • 14V to 20V DC input
  • PCI Express edge connector power
  • On-board power measurement circuitry

Arria II GX-260 FPGA Development Kit CD-ROM

  • Design examples
    • PCI Express High-Performance Reference Design
    • PCI Express-to-DDR2 SDRAM Reference Design

Altera’s complete Design Suite DVD

  • Quartus II Software Development Kit Edition, includes support for Arria II GX FPGAs
  • Nios II Embedded Design Suite
  • MegaCore® IP Library includes PCI Express, Triple Speed Ethernet, SDI, and DDR3 High-Performance Controller IP cores
    • IP evaluation available through OpenCore Plus

  • Size:216X107mm

Download

Documents

TitleVersionSize(KB)Date AddedDownload
A2GX_260_User_manual16052010-12-01

CD-ROM

TitleVersionSize(KB)Date AddedDownload
A2GX-260 CD-ROM 2010-12-01

Please note that all the source codes are provided "as is". For further support or modification, please contactTerasic Support and your request will be transferred to Terasic Design Service.
More resources about IP and Dev. Kit are available on Altera User Forums.


The Arria II GX-260  includes:

    

 


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