Arria II GX-260 FPGA development board

Arria II GX EP2AGX260 FPGA

·         256,000 logic elements (LEs)

·         102,600 adaptive logic modules (ALMs)

·         11,756 Kb on-chip memory

·         16 high-speed transceivers

·         6 phase-locked loops (PLLs)

·         736 18x18 multipliers

·         0.9V core power

Max® II EPM2210F256 CPLD

·         2.5V core power

On-board Ports

·         Two HSMC expansion ports

·         One gigabit Ethernet port

PCI Express x8 Edge Connector

·         Support connection speed of Gen1 at 2.5Gbps/lane

·         Connection established with PC motherboard with x8 PCI Express slot

On-board Memory

·         128MB 16bit DDR3 device

·         1GB 64bit DDR2 SO-DIMM

·         2MB SSRAM

·         64MB FLASH

FPGA Configuration Circuitry

·         MAX II CPLD and flash fast passive parallel configuration

·         On-board USB-Blaster™ circuitry using the Quartus II Programmer

On-Board Clocking Circuitry

·         Four on-board oscillators

o    100MHz

o    Programmable oscillator, default frequency 125MHz

o    Programmable oscillator, default frequency 100MHz

o    155.52MHz

·         SMA connectors for external LVPECL clock input

·         SMA connector for clock output

·         DIP switches

Power Supply

·         14V to 20V DC input

·         PCI Express edge connector power

·         On-board power measurement circuitry

Arria II GX-260 FPGA Development Kit CD-ROM

·         Design examples

o    PCI Express High-Performance Reference Design

o    PCI Express-to-DDR2 SDRAM Reference Design

Altera’s complete Design Suite DVD

·         Quartus II Software Development Kit Edition, includes support for Arria II GX FPGAs

o    Quartus II software license is not included as part of this kit

·         Nios II Embedded Design Suite

·         MegaCore® IP Library includes PCI Express, Triple Speed Ethernet, SDI, and DDR3 High-Performance Controller IP cores

o    IP evaluation available through OpenCore Plus

General User I/O

·         LEDs/displays

o    Four user LEDs

o    Two-line character LCD display

o    One configuration-done LED

o    One HSMC interface transmit/receive LED

o    Three PCI Express LEDs

o    Five Ethernet LEDs

Push-buttons

·         One user reset (CPU reset)

·         One MAX II CPLD reset

·         One load image (program FPGA from flash)

·         One image select (select image to load from flash)

·         Two general user push-buttons

DIP switches

·         Four user DIP switches

·         Eight MAX II device control DIP switches