Featured devices

• Stratix IV GX EP4SGX230KF40C2N FPGA or,
• Stratix IV GX EP4SGX530KH40C2N FPGA

Configuration status and set-up elements

• Fast passive parallel (FPP) configuration via a MAX^® II EPM2210 CPLD and flash memory
• On-board USB-Blaster^TM download cable using Quartus II Programmer

Clocks

• On-board clock oscillators: 50 MHz, 100 MHz, 125 MHz, 148.5 MHz, 155.52 MHz, and 156.25 MHz
• SMA connectors for external clock input
• SMA connectors for clock output

General user input/output

• LEDs
• LCD display
• Push-button and dual in-line package (DIP) switches

Memory devices

• 512-MB DDR3 SDRAM with a 64-bit data bus
• 128-MB DDR3 SDRAM with a 16-bit data bus
• Two 4-MB QDR II+ SRAMs with 18-bit data buses
• 64-MB sync flash and 2-MB SSRAM

Component and interfaces

• PCI Express x8 edge connector
• 10/100/1000BASE-T Ethernet PHY with RJ-45 connector
• Two HSMC connectors
• HDMI video output
• 3G-SDI video input and output
• Power measurement circuitry
• Temperature measurement circuitry

Power

• Laptop DC input
• PCI Express edge connector power
• Power measurement circuitry

Other features

• PCI Express half-length, full-height (6.6" x 4.376") board format
• RoHS compliant

Altera Stratix IV GX FPGA Development Kit Block Diagram

Documents

Title	Version	Size(KB)	Date Added	Download
Stratix IV GX FPGA Development Kit User Guide (PDF)			2013-01-11
Stratix IV GX FPGA Development Board Reference Manual (PDF)			2013-01-11
Stratix IV GX FPGA Development Kit, 530 Edition User Guide (PDF)			2013-01-11
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual (PDF)			2013-01-11

CD-ROM

Title	Version	Size(KB)	Date Added	Download
Kit installation			2013-01-11

Reference Designs

Title	Version	Size(KB)	Date Added	Download
Serial RapidIO to TI 6488 DSP Reference Design			2013-01-11
PCI Express High-Performance Reference Design			2013-01-11
POS-PHY L4 SPI-4.2 Loopback Design Example			2013-01-11
PCI Express to External Memory Reference Design			2013-01-11
10-Gbps Ethernet Hardware Demonstration Reference Design			2013-01-11

Please note that all the source codes are provided "as is". For further support or modification, please contactTerasic Support and your request will be transferred to Terasic Design Service.
More resources about IP and Dev. Kit are available on Altera User Forums.

• Stratix IV GX FPGA Development Kit soft content
  • Design examples
    • Board Update Portal featuring the Nios^® II processor web server and remote system update
    • Board Test System
  • Complete documentation
• Altera's Complete Design Suite (download from Altera Download Center )
  • Quartus II software includes support for Stratix IV FPGAs and HardCopy IV ASICs
    • 1-year license included
  • Nios II Embedded Design Suite
  • MegaCore^® intellectual property (IP) library includes PCI Express, Triple-Speed Ethernet, SDI, and DDR3 High-Performance Controller MegaCore IP cores
    • IP evaluation available through OpenCore Plus
• Loopback and debug HSMCs
• Power adapter and cables