회사소개
협력사
Terasic-FGPA Series
All FPGA Main Board
- Stratix III, IV, V
- Arria II. V
- Cyclone II, III, IV, V
- Bundle Solution
- USB Blaster
- max10
Daughter Card
- Interface conversion
- Video & Image
- Networking
- AD/DA
- Capsense
- Multimedia
- RF
SOC Platform
Microtronix-FPGA Series
IP Core
HSMC Daughter Card
Configurable Processor
FPGA Board
- HD Dev Solution
University Training Classes
Universities Classes using the DE2 Series
Altera 온라인 데모
Design Software
Embedded Processors
Licensing
Bundled Solutions
ARM Development Kit
ARM Development Kit
Single board computers
Computer-on-Module
AS 수리
dimocore.com/terasicrepair
자료실
고객센터
공지사항
문의게시판
 
 
Terasic-FGPA Series > All FPGA Main Board > Stratix III, IV, V
   
Terasic TR4 FPGA Development Kit 
 
가    격 : 견적문의
중    량 : 100g

The TR4 Development Board provides the ideal hardware platform for system designs that demand high-performance, serial connectivity, and advanced memory interfacing. Developed specifically to address the rapidly evolving requirements in many end markets for greater bandwidth, improved jitter performance, and lower power consumption, the TR4 is powered by the Stratix® IV GX device and supported by industry-standard peripherals, connectors and interfaces that offer a rich set of features that is suitable for a wide range of compute-intensive applications.

The TR4 is supported by multiple reference designs and six High-Speed Mezzanine Card (HSMC) connectors that allow scaling and customization with mezzanine daughter cards. For large-scale ASIC prototype development, multiple TR4s can be stacked together to create an easily-customizable multi-FPGA system.

 

FPGA Devices

Stratix IV GX EP4SGX230

  • 228,000 logic elements (LEs)
  • 17,133K total memory Kbits
  • 1,288 18x18-bit multipliers blocks
  • 2 PCI Express hard IP blocks
  • 744 user I/Os
  • 8 phase locked loops (PLLs)

Stratix IV GX EP4SGX530

  • 531,200 logic elements (LEs)
  • 27,376K total memory Kbits
  • 1,024 18x18-bit multipliers blocks
  • 4 PCI Express hard IP Blocks
  • 744 user I/Os
  • 8 phase locked loops (PLLs)

FPGA Configuration

  • MAXII CPLD EPM2210 System Controller and Fast Passive Parallel (FPP) configuration
  • On-board USB Blaster for use with the Quartus II Programmer
  • Programmable PLL timing chip configured via MAX II CPLD
  • Supports JTAG mode

Memory Devices

  • 64MB Flash with a 16-bit data bus
  • 2MB SSRAM (512K x 32)

DDR3 SO-DIMM Socket

  • Up to 4GB capacity
  • Maximum memory clock rate at 533MHz
  • Theoretical bandwidth up to 68Gbps

Buttons, Switches and LEDs

  • 4 user-controllable LEDs
  • 4 user-defined
  • 4 slide switches for user-defined inputs

On-Board Clocks

  • 50MHz oscillator

SMA Connectors

  • SMA connector pair for differential clock inputs
  • SMA connector pair for differential clock outputs
  • SMA connector for clock output
  • SMA connector for external clock input

Two PCI Express x4 Connectors

  • Support connection speed of Gen1 at 2.5Gbps/lane to Gen2 at 5.0Gbps/lane
  • High-speed transceiver channels up to 6.5 Gbps
  • Support downstream mode

Six 172-pins High Speed Mezzanine Card (HSMC)

  • 6 HSMC connectors
  • Configurable I/O standards - 1.5V, 1.8V, 2.5V, 3.0V
  • Total of 16 high-speed transceivers up to 6.5 Gbps
  • Among HSMC Port A to D, there are 55 true LVDS TX channels to 1.6Gbps and 17 emulated LVDS TX channels up to 1.1Gbps whereas there are 9 additional TX channels from HSMC Port E.

Two 40-pin Expansion Headers

  • 72 FPGA I/O pins; 4 power and ground lines
  • Configurable I/O standards - 1.5V, 1.8V, 2.5V, 3.0V
  • Shares pins with HSMC Port

Power

  • Standalone DC 19V input

Block Diagram

    

  • Size:182.36 x 210.82 mm

Download

Documents

TitleVersionSize(KB)Date AddedDownload
Using the Design Security Feature in TR41.016032014-06-06
TR4 User Manual141642014-03-18

Daughter Card Demonstations

TitleVersionSize(KB)Date AddedDownload
NET 2012-08-10
ADA 2012-07-16
AHA 2012-07-16
D5M 2012-07-16
DCC 2012-07-16
HDMI 2012-07-16
ICB 2012-07-16
MTL 2012-07-16
MTLC 2012-07-16
SATA 2012-07-16
SDI 2012-07-16
XTS 2012-07-16
DVI 2012-07-16

CD-ROM

TitleVersionSize(KB)Date AddedDownload
TR4-CD-ROM1.0.5 2012-04-09
PCIe Driver and Applicaiton Software (Windows7/XP x 64-bits/32-bits) 2012-04-01

Please note that all the source codes are provided "as is". For further support or modification, please contactTerasic Support and your request will be transferred to Terasic Design Service.
More resources about IP and Dev. Kit are available on Altera User Forums.

 

TR4 Tools

TR4 Control Panel – allows users to access various components on the TR4 board from a host computer.

TR4 Control Panel

TR4 System Builder – a powerful tool comes with the TR4 board. This tool will allow users to create a Quartus II project file on their custom design for the TR4 board. The top-level design file, pin assignments, and I/O standard settings for the TR4 board will be generated automatically by the TR4 System Builder. In addition, through the HSMC connectors you can select various daughter cards in conjunction with the TR4 using the TR4 System Builder.

TR4 System Builder

The generated Quartus II project files include the following:

  • Quartus II Project File (.qpf)
  • Quartus II Setting File (.qsf)
  • Top-Level Design File (.v)
  • External PLL Contorller (.v)
  • Synopsis Design Constraints file (.sdc)
  • Pin Assignment Document (.htm)

TR4 Reference Designs

  • Breathing LEDs
  • External Clock Generator
  • High Speed Mezzanine Card Connector Test
  • DDR3 Nios II Read/Write Loopback Test
  • DDR3 HDL Read/Write Test
  • PCI Express Fundamental Communication
  • PCI Express Image Processing Application

The TR4 package includes:



Resources  Demo

 


상호명
: (주)우림티앤아이   대표자명 : 김석범   사업자등록번호 : 211-87-88913  이메일 : jun@woorimtni.co.kr
본사 : 서울 강남구 봉은사로 129 거평타운 1204호 대표전화 : 82-2-512-7661  팩스 : 82-2-512-7662
Copyright(C) 2011 Woorimtni Technologies All Rights Reserved.