The TR5-Lite Stratix V FPGA Development Kit a slim form-factor PCIe board that features maximum power in a minimum size. Perfect for 1U chassis servers and other stringent environments, the TR5-Lite includes high speed SFP+ interfaces and high-bandwidth memory architecture for high performance computing, cloud systems, and ultra low-latency trading.

The TR5-Lite Board

Altera Stratix® V GX FPGA (5SGXEA7N2F45C2)

• JTAG header for FPGA programming
• Fast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory

General user input / output:

• 4 LEDs
• 1 LED Array
• 2 push-buttons
• 2-position DIP switch

On-Board Clock

• 50MHz Oscillator
• Programmable oscillators Si570 and CDCM61004

Memory

• 36MB 550MHZ QDRII+ SRAM
• 2GB 667MHz DDR3 SDRAM
• 256MB FLASH

Communication Ports

• Two SFP+ connectors
• One Serial ATA (SATA II) host port
• PCI Express (PCIe) x8 edge connector
• One RS422 transceiver with 1394 connector

System Monitor and Control

• Temperature sensor
• Fan control

Power

• PCI Express 6-pin power connector, 12V DC Input
• PCI Express edge connector power

Mechanical Specification

• PCI Express low-profile and half-length

Connectivity

  Demonstration

 

 

• Size：64.4 * 167.6 mm

Download

Documents

Title	Version	Size(KB)	Date Added	Download
TR5-Lite User Manual		2907	2013-11-28

CD-ROM

Title	Version	Size(KB)	Date Added	Download
TR5-Lite CD-ROM	1.0.0		2013-11-28

Please note that all the source codes are provided "as is". For further support or modification, please contactTerasic Support and your request will be transferred to Terasic Design Service.
More resources about IP and Dev. Kit are available on Altera User Forums.